Previous Year Questions

(i) What is meant by data dependence?

Data dependence is a situation where an instruction relies on the result produced by a preceding instruction. For example, if Instruction A writes to register R1 and Instruction B reads R1, B is data-dependent on A. This is the fundamental cause of Data Hazards (RAW, WAW, WAR) in pipelined processors.

(ii) Which page replacement algorithm suffers from Belady's anomaly?

FIFO (First-In, First-Out). Belady's anomaly is the counter-intuitive phenomenon where increasing the number of page frames can actually increase the number of page faults. LRU and Optimal algorithms are "stack algorithms" and do not exhibit this anomaly.

(iii) Which architecture is/are suitable for realizing SIMD?

Array Processors and Vector Processors. Both apply a single instruction to multiple data elements simultaneously. Array processors use multiple identical Processing Elements (PEs) working in lockstep. Vector processors use deeply pipelined functional units to process entire vectors.

(iv) What is meant by Branch Prediction?

Branch Prediction is a hardware technique where the processor guesses the outcome of a conditional branch (taken or not taken) and its target address before the branch condition is actually evaluated. This allows the pipeline to continue fetching instructions speculatively, avoiding stalls. Modern predictors achieve >95% accuracy.

(v) The throughput of a superscalar processor is ____.

Greater than 1 instruction per clock cycle. An n-way superscalar can theoretically complete up to n instructions per cycle (IPC > 1).

(vi) Which unit is responsible for translation of logical address to physical address?

Memory Management Unit (MMU). It uses the Page Table (cached in the TLB) to translate virtual page numbers to physical frame numbers.

(vii) The ____ plays a very vital role in case of superscalar processors.

Instruction Fetch/Decode/Issue unit. This front-end must fetch, decode, and dispatch multiple instructions per cycle. A bottleneck here starves the execution units.

(viii) The set of loosely connected computers are called as ____.

Cluster (also called a Distributed System or Multicomputer). Each node has its own private memory and OS; they communicate via message passing.

(ix) Write the equation for Amdahl's Law.

Where P = fraction of the program that can be parallelized, N = number of processors. The term (1 − P) is the sequential bottleneck that limits maximum speedup.

(x) Write the statement for memory inclusion property.

Inclusion Property: Any block of data present in a higher-level (smaller, faster) cache (e.g., L1) must also be present in every lower-level (larger, slower) cache (e.g., L2, L3). This simplifies coherence protocols because snooping only the outermost cache is sufficient.

(xi) What is meant by instruction level parallelism?

Instruction Level Parallelism (ILP) is the measure of how many instructions in a program can be executed simultaneously because they are independent of each other. ILP is exploited by pipelining, superscalar execution, VLIW, and out-of-order execution. Typical ILP in real programs: 2–5.

(xii) In tightly coupled systems, the microprocessors share ____.

A common main memory. This shared-memory architecture allows fast communication between processors through shared variables, coordinated by cache coherence protocols.

Given: A 4-segment pipeline with delays: S1 = 40 ns, S2 = 25 ns, S3 = 45 ns, S4 = 45 ns. Interface register delay = 5 ns. Number of tasks = 100.

Step 1 — Cycle Times:

• Non-pipeline cycle time (t_n): All segments execute sequentially for each task.
  t_n = 40 + 25 + 45 + 45 = 155 ns
• Pipeline cycle time (t_p): Determined by the slowest segment + register delay.
  t_p = Max(40, 25, 45, 45) + 5 = 45 + 5 = 50 ns

Step 2 — Execution Time for 100 Tasks:

• Non-pipeline: Each task takes the full 155 ns sequentially.
  
  T_non = n × t_n = 100 × 155 = 15,500 ns
• Pipeline: The first task takes k cycles to fill the pipeline, then each subsequent task completes every cycle.
  
  T_pipe = (k + n − 1) × t_p = (4 + 100 − 1) × 50 = 103 × 50 = 5,150 ns

Step 3 — Real Speedup:

Step 4 — Maximum Speedup:

As n → ∞, the pipeline startup cost (k cycles) becomes negligible:

Note: The theoretical maximum speedup for k stages is k = 4, but because the stages are unbalanced (25 ns vs 45 ns) and the register delay adds overhead, the actual maximum is only 3.1.

Given: Clock Rate = 1.8 GHz. Instruction mix:

• ALU operations: 40% frequency, 1 clock cycle
• Load instructions: 20% frequency, 2 clock cycles
• Store instructions: 10% frequency, 2 clock cycles
• Branch instructions: 30% frequency, 2 clock cycles

Step 1 — Calculate CPI (Cycles Per Instruction):

CPI = (0.40 × 1) + (0.20 × 2) + (0.10 × 2) + (0.30 × 2)

CPI = 0.40 + 0.40 + 0.20 + 0.60

Step 2 — Calculate MIPS Rating:

MIPS = (1.8 × 10⁹) / (1.6 × 10⁶)

MIPS = 1,800 / 1.6

Interpretation:

• A CPI of 1.6 means, on average, each instruction takes 1.6 clock cycles. The ideal for a pipelined processor is CPI = 1.0, so this machine has a 60% overhead due to multi-cycle operations.
• At 1,125 MIPS, this processor executes about 1.125 billion instructions per second.
• CPU Execution Time for a program with N instructions = N × CPI / Clock Rate = N × 1.6 / (1.8 × 10⁹) seconds.

Superscalar Processor:

A superscalar processor is a CPU that implements instruction-level parallelism (ILP) within a single processor core. It can fetch, decode, and dispatch multiple instructions simultaneously to multiple parallel execution units (integer ALUs, FP units, load/store units) in a single clock cycle. The key hardware components enabling this are:

• Multiple Functional Units: Several ALUs, FP units, and memory ports operating in parallel.
• Dynamic Scheduling: Hardware (reservation stations, scoreboard) detects independent instructions and dispatches them out-of-order.
• Register Renaming: Eliminates false dependencies (WAW, WAR) by mapping architectural registers to a larger pool of physical registers.
• Speculative Execution: Executes past unresolved branches using branch prediction.

Examples: Intel Core i7 (6-wide issue), AMD Ryzen (6-wide), Apple M-series (8-wide).

Advantages of Vector Computers:

• Reduced Instruction Overhead: A single vector instruction (e.g., VADDPS) operates on an entire array of 64 or more elements, dramatically reducing the number of instructions fetched, decoded, and issued compared to scalar code that requires a loop.
• Highly Efficient Pipelining: Vector functional units are deeply pipelined. Once the pipeline is filled, one result is produced every clock cycle. There are no data hazards between elements of the same vector operation.
• Memory Bandwidth Optimization: Vector processors use techniques like vector stride and bank interleaving to sustain high memory bandwidth, hiding individual access latency behind pipelined memory systems.
• Simplified Control Logic: No need for dynamic scheduling or branch prediction within vector operations — the hardware simply processes element after element.
• Ideal for Scientific Computing: Matrix operations, FFT, weather simulation, molecular dynamics, and image/video processing all exhibit regular, predictable data access patterns that vector architectures exploit perfectly.

Static Networks vs Dynamic Networks:

• Static Networks (Fixed Topology): Point-to-point links directly connect processors. The topology is fixed at design time and cannot be reconfigured. Each processor has a fixed set of neighbors. Examples: Ring, Mesh/Torus, Hypercube, Tree. Used in tightly coupled multiprocessors.
• Dynamic Networks (Switched): Communication paths are established dynamically using switches. The network can route messages between any two processors through configurable switching elements. Examples: Crossbar switch, Omega network, Butterfly network, Multistage Interconnection Networks (MINs). Used in shared-memory multiprocessors and interconnection fabrics.

Key Differences:

• Reconfigurability: Static — No; Dynamic — Yes.
• Cost: Static — Lower (just wires); Dynamic — Higher (switching elements).
• Bandwidth: Static — Limited by neighbor links; Dynamic — Can provide any-to-any connectivity.
• Latency: Static — Depends on network diameter; Dynamic — Depends on switch stages.

Hypercube Interconnection (n = 3):

A hypercube of dimension n connects 2ⁿ nodes. For n = 3: 2³ = 8 nodes, labeled 000 through 111 in binary.

Connection Rule: Two nodes are directly connected if and only if their binary addresses differ in exactly one bit position.

• Node 000 connects to: 001 (bit 0), 010 (bit 1), 100 (bit 2)
• Node 001 connects to: 000, 011, 101
• Node 010 connects to: 000, 011, 110
• Node 011 connects to: 001, 010, 111
• Node 100 connects to: 000, 101, 110
• Node 101 connects to: 001, 100, 111
• Node 110 connects to: 010, 100, 111
• Node 111 connects to: 011, 101, 110

Properties: Each node has exactly n = 3 neighbors. The network diameter (max hops between any two nodes) = n = 3. Total links = n × 2ⁿ / 2 = 3 × 8 / 2 = 12 links. The topology forms a 3D cube.

All three architectures aim to increase instruction throughput beyond a simple pipelined processor. They differ in how they achieve parallelism:

1. Superscalar (Spatial Parallelism):

• Uses multiple parallel execution units to issue and complete more than one instruction per clock cycle.
• The clock period equals the delay of one pipeline stage (same as a normal pipeline).
• An m-way superscalar ideally achieves m instructions per cycle.
• Example: If base CPI = 1.0, a 2-way superscalar targets CPI = 0.5 (IPC = 2).

2. Super-Pipelined (Temporal Parallelism):

• Divides each pipeline stage into n sub-stages, creating a deeper pipeline with a proportionally higher clock frequency.
• Still issues only one instruction per cycle, but the cycle is n times shorter.
• An n-degree super-pipelined processor achieves a throughput equivalent to issuing n instructions per normal cycle.
• Trade-off: Deeper pipelines suffer larger branch misprediction penalties (more stages to flush).

3. Superscalar-Super-Pipelined (Combined):

• Combines both techniques: multiple execution units (m-way) AND a deep pipeline (n sub-stages).
• Theoretically achieves m × n instructions per normal pipeline cycle.
• This is what modern high-performance processors actually use — e.g., Intel Core i7 is a 6-wide superscalar with a 14–19 stage pipeline.

Key Comparison:

• Superscalar: Multiple instructions issued per cycle; normal clock speed.
• Super-pipelined: One instruction per cycle; faster clock speed.
• Combined: Multiple instructions per cycle; faster clock speed. Maximum throughput but maximum complexity.

(a) Tightly Coupled vs. Loosely Coupled Systems:

Aspect	Tightly Coupled (Multiprocessor)	Loosely Coupled (Multicomputer / Cluster)
Memory	Shared common main memory (global address space)	Each processor has its own private local memory
Communication	Through shared memory (load/store)	Through message passing (send/receive) over a network
OS	Single OS manages all processors	Each node runs its own OS instance
Latency	Low (shared memory access: ~100 ns)	High (network message: ~1–100 μs)
Scalability	Limited (bus/memory contention at ~64 processors)	Highly scalable (thousands of nodes)
Programming Model	Easier (shared variables, threads, OpenMP)	Harder (explicit message passing, MPI)
Coherence	Requires cache coherence protocols (MESI)	Not needed (no shared caches)
Examples	Multi-core CPUs, SMP servers	Beowulf clusters, Google's data centers

(b) Multiprocessor Architectures — UMA, NUMA, COMA:

1. UMA (Uniform Memory Access):

• Also called Symmetric Multiprocessor (SMP).
• All processors are connected to a single shared memory through a common bus or crossbar switch.
• Every processor has equal access time to every memory location — hence "uniform".
• Advantages: Simple programming model (all memory looks the same); fair load distribution.
• Disadvantages: The shared bus becomes a bottleneck as more processors are added. Practical limit: ~8–16 processors.
• Coherence: Maintained via snoopy bus protocols (MESI).

2. NUMA (Non-Uniform Memory Access):

• Each processor has its own local memory, but can also access other processors' memory through an interconnection network.
• Accessing local memory is fast (~100 ns); accessing remote memory is slower (~300–500 ns) — hence "non-uniform".
• Advantages: Scales to hundreds of processors because there is no single shared bus. Each processor-memory pair can operate independently.
• Disadvantages: Programming is more complex — data placement matters. Poor data locality causes frequent expensive remote accesses.
• Coherence: Uses directory-based protocols (since snooping doesn't scale).
• Example: AMD EPYC (multi-socket), Intel Xeon Scalable.

3. COMA (Cache-Only Memory Architecture):

• A specialization of NUMA where there is no traditional main memory. Each processor's local memory acts as a large cache.
• Data migrates dynamically to whichever processor's local cache needs it most, based on access patterns. There is no fixed "home" node for any block.
• Advantages: Automatically optimizes data placement — frequently accessed data migrates close to the accessing processor, reducing latency.
• Disadvantages: Very complex hardware for managing data migration, replication, and ensuring at least one copy always exists. If the last copy is evicted, it must be written back somewhere (requires a "home" protocol extension).
• Example: KSR-1 (Kendall Square Research).

(a) Page Fault:

A Page Fault is an exception (interrupt) generated by the MMU hardware when a program accesses a virtual page whose valid bit in the page table is 0 — meaning the page is currently on disk (swap space), not in physical RAM. The OS page fault handler then: (1) selects a victim page if all frames are full, (2) writes the victim to disk if dirty, (3) reads the requested page from disk into the freed frame, (4) updates the page table entry, (5) restarts the faulting instruction.

(b) Page Replacement — Step-by-Step Trace:

Reference String: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6 (20 references). Assume 3 frames.

FIFO (First-In, First-Out):

Replace the page that has been in memory the longest (oldest arrival).

Ref	1	2	3	4	2	1	5	6	2	1	2	3	7	6	3	2	1	2	3	6
F1	1	1	1	4	4	4	4	6	6	6	6	3	3	3	3	2	2	2	2	6
F2		2	2	2	2	1	1	1	2	2	2	2	7	7	7	7	1	1	1	1
F3			3	3	3	3	5	5	5	1	1	1	1	6	6	6	6	6	3	3
F/H	F	F	F	F	H	F	F	F	F	F	H	F	F	F	H	F	F	H	F	F

LRU (Least Recently Used): Replace the page that hasn't been used for the longest time.

Optimal (Belady's Algorithm): Replace the page that won't be used for the longest time in the future.

Comparison: Optimal ≤ LRU ≤ FIFO in terms of fault rates, as expected. Optimal is the theoretical best but is not implementable in practice (requires future knowledge). LRU is a practical near-optimal approximation.

(c) Virtual Memory through Segmentation:

Segmentation divides the virtual address space into variable-sized logical units called segments, each corresponding to a logical entity like:

• Code segment (program instructions)
• Data segment (global variables)
• Stack segment (function call frames)
• Heap segment (dynamic allocations)

Address Translation: A virtual address is a pair: (Segment Number, Offset). The OS maintains a Segment Table for each process. Each entry contains:

• Base Address: Starting physical address of the segment.
• Limit (Length): Size of the segment. The hardware checks that Offset < Limit to enforce protection.
• Protection bits: Read/Write/Execute permissions.

Physical Address = Base + Offset (if Offset < Limit, else → Segmentation Fault).

Advantage over paging: Segments match the logical structure of a program, making protection and sharing easier. Disadvantage: Variable-sized segments cause external fragmentation in physical memory.

(a) SIMD Array Processor Architecture [5]:

SIMD (Single Instruction, Multiple Data) is one of Flynn's four classifications. In an SIMD architecture, a single control unit broadcasts one instruction to multiple Processing Elements (PEs) that operate on different data elements simultaneously.

• Structure: One Control Unit (CU) fetches and decodes instructions. Multiple PEs (each with its own local memory or register set) execute the same operation on their own private data. An interconnection network connects PEs to a shared memory or to each other.
• Execution Model: In each clock cycle, every active PE performs the identical operation (e.g., ADD) but on different data operands. PEs can be selectively masked (disabled) for conditional operations — inactive PEs simply idle during that instruction.
• Examples: ILLIAC IV (historic), modern GPU shader cores, Intel SSE/AVX SIMD instructions.
• Advantages: Very efficient for data-parallel workloads (image processing, matrix operations, physics simulations). Minimal control overhead since only one instruction fetch/decode is needed for all PEs.
• Limitations: Poor performance for control-heavy, irregular workloads. PE utilization drops when many PEs are masked due to conditional code (divergence).

(b) Vector Stride and Vectorization [2]:

• Vector Stride: The distance (in memory words or bytes) between consecutive elements of a vector as stored in memory. A unit stride (stride = 1) means elements are contiguous — the best case for memory bandwidth. A non-unit stride (e.g., accessing every 5th element of a 2D array stored in row-major order) causes elements to be scattered, potentially causing bank conflicts and reducing memory throughput.
• Vectorization: The process (done by the compiler or programmer) of converting a scalar loop (processing one element at a time) into vector instructions (processing an entire vector at a time). Example: converting for(i=0; i<64; i++) C[i] = A[i] + B[i]; into a single VADD V3, V1, V2 instruction.

(c) Scalar Processor vs. Vector Processor [2]:

• Scalar Processor: Operates on one data element per instruction. An ADD instruction adds two scalar registers (e.g., R1 = R2 + R3). To add 64 pairs of numbers, 64 separate ADD instructions must be fetched, decoded, and executed — generating 64× the instruction overhead.
• Vector Processor: Operates on an entire vector (array of data elements) per instruction. A single VADD instruction adds two vector registers element-by-element (e.g., V3[0..63] = V1[0..63] + V2[0..63]). Only one fetch/decode is needed for 64 operations, vastly reducing control overhead.

(d) Vector Gather and Scatter Operations [6]:

Gather and Scatter are special vector memory operations designed to handle indirect (indexed) memory access patterns — situations where vector elements are not stored contiguously in memory.

Gather (Indexed Load):

• Purpose: Collect scattered data elements from arbitrary memory locations into a dense, contiguous vector register.
• Mechanism: Uses an index vector register (containing memory addresses or offsets) to specify which memory locations to read. The hardware fetches each element individually and packs them into the destination vector register.
• Example: Given Index = [3, 7, 1, 9] and Memory M: VGATHER V1, M, V_index loads V1 = [M[3], M[7], M[1], M[9]].
• Use Case: Sparse matrix operations, histogram computation, look-up table access.

Scatter (Indexed Store):

• Purpose: Distribute elements from a dense vector register to arbitrary (non-contiguous) memory locations.
• Mechanism: Uses an index vector to specify where each element of the source vector register should be written in memory.
• Example: Given V1 = [a, b, c, d] and Index = [3, 7, 1, 9]: VSCATTER M, V1, V_index writes M[3]=a, M[7]=b, M[1]=c, M[9]=d.
• Challenge: Scatter operations can have write conflicts if two indices point to the same memory location. Hardware must handle this carefully (usually last-write-wins).

Performance Note: Gather/Scatter operations are significantly slower than unit-stride vector loads/stores because each element requires a separate, potentially non-sequential memory access. Modern vector processors optimize these using memory bank interleaving and address coalescing.

(a) Cache Coherency [2]:

Cache Coherency is the discipline that ensures all processors in a multiprocessor system observe a consistent view of memory. Specifically, if Processor A writes value X to address 0x1000, then any subsequent read of 0x1000 by Processor B must return X (or a later value), not a stale cached copy. Without coherence, parallel programs produce incorrect results.

Formal Conditions (for coherence to hold):

• Write Propagation: A write to a shared block must eventually become visible to all processors.
• Write Serialization: All processors see writes to the same address in the same order.

(b) MESI Protocol [3]:

MESI is the most widely used snoopy cache coherence protocol. Each cache line has a 2-bit state tag:

• Modified (M): This cache has the only valid copy, and it has been written (dirty). Main memory is stale. Must write-back before another cache can use it.
• Exclusive (E): This cache has the only copy, and it is clean (matches memory). Can transition to M on a write without bus traffic — a major optimization.
• Shared (S): This block may exist in multiple caches. All copies and main memory are consistent. A write requires an invalidation broadcast first.
• Invalid (I): The cache line is not valid. Any read triggers a miss.

Key Transitions:

• I → E: Read miss, no other cache has the block → fetch from memory, enter Exclusive.
• I → S: Read miss, another cache has the block → fetch, enter Shared.
• E → M: Local write → silently transition (no bus traffic needed!).
• S → I: Snooped write from another processor → invalidate local copy.
• M → S: Snooped read from another processor → supply data, write-back, enter Shared.

(c) Snoopy Bus Protocol (Detailed) [6]:

Snoopy protocols rely on a shared bus that all cache controllers monitor (snoop).

• Bus Architecture: All processors and their caches are connected to a single shared bus. All memory transactions (reads, writes, invalidations) are broadcast on this bus.
• Snooping Mechanism: Every cache controller continuously monitors the bus. When it sees a transaction for a block it holds, it takes appropriate action (invalidate, update, or supply data).
• Write-Invalidate Protocol: When a processor writes to a shared block, it broadcasts an invalidation message. All other caches holding that block mark their copies as Invalid. This is the most common approach (used in MESI, MOESI).
• Write-Update (Write-Broadcast) Protocol: When a processor writes, it broadcasts the new data value. All other caches update their copies immediately. Reduces future read misses but generates much more bus traffic.
• Advantages of Snooping: Simple hardware implementation; low latency for small systems (everything is on the bus).
• Limitations: The shared bus has finite bandwidth. Beyond ~16–32 processors, bus contention becomes a critical bottleneck. Not suitable for large-scale systems — directory-based protocols are used instead.

(d) Synchronization in Multiprocessors [4]:

Synchronization ensures that multiple processors accessing shared data do so in a coordinated manner, preventing race conditions and ensuring correctness.

• Hardware Primitives:
  • Test-and-Set (TAS): Atomically reads a memory location, returns the old value, and sets it to 1. Used to implement spin-locks: while(TAS(&lock) == 1) { /* spin */ }.
  • Compare-and-Swap (CAS): Atomically compares a memory location to an expected value; if they match, writes a new value. More flexible than TAS; foundation of lock-free data structures.
  • Load-Linked / Store-Conditional (LL/SC): LL reads a value; SC writes only if no other processor has written to that address since the LL. Avoids the ABA problem of CAS.
• Software Constructs (built on hardware primitives):
  • Locks (Mutexes): Only one processor can hold the lock; others spin or block.
  • Barriers: All processors must arrive at the barrier before any can proceed past it. Used to synchronize phases of computation.
  • Semaphores: Counting mechanism that allows a specified number of concurrent accesses.
• Performance Concern: Naive spin-locks generate heavy bus traffic as all spinning processors repeatedly issue TAS operations. Test-and-Test-and-Set (spin on a cached copy, only issue TAS when the lock appears free) reduces bus contention significantly.

(a) VLIW Architecture (Detailed) [6]:

VLIW (Very Long Instruction Word) is a processor architecture that achieves ILP through static (compile-time) scheduling rather than dynamic (hardware) scheduling.

• Instruction Format: Each instruction word is very wide (128–1024+ bits) and is divided into fixed operation slots. Each slot corresponds to a specific functional unit (e.g., Slot 1 → Integer ALU, Slot 2 → FP Multiply, Slot 3 → Load/Store, Slot 4 → Branch).
• Compiler Responsibility: The compiler must analyze the entire program at compile time to find groups of independent operations that can execute in parallel. It packs these into the operation slots of a single VLIW instruction. If fewer independent operations exist than slots, the remaining slots are filled with NOPs.
• Hardware Simplicity: The processor hardware is dramatically simpler than a superscalar. There is no need for: dependency checking logic, reservation stations, reorder buffers, register renaming hardware, or branch speculation logic. The hardware simply reads the wide instruction and dispatches each slot to its functional unit.
• Scheduling Techniques used by VLIW Compilers:
  • Trace Scheduling: The compiler identifies the most frequently executed paths (traces) through the program and schedules operations along these paths aggressively, adding compensation code for mispredicted paths.
  • Software Pipelining (Modulo Scheduling): Overlaps iterations of loops by interleaving operations from different iterations into the same VLIW instruction.
  • Predicated Execution: Converts branches into predicated (conditional) operations, eliminating branch penalties entirely.
• Examples: Intel Itanium (IA-64) with "bundles" of 3 operations; TI TMS320C6000 DSPs with 8 operation slots; Transmeta Crusoe (translated x86 to VLIW internally).

(b) Advantages and Disadvantages of VLIW [5]:

Advantages:

• Simple Hardware: No dynamic scheduling, no register renaming, no reorder buffer → smaller chip area, lower power, and potentially higher clock speeds.
• Deterministic Execution: The execution timeline is known at compile time → easier to analyze performance and real-time constraints.
• Compiler's Global View: The compiler can analyze the entire program (across basic blocks, functions) to find parallelism that hardware with a limited instruction window cannot see.
• Lower Power: The simplified hardware results in significantly lower power consumption, making VLIW ideal for embedded and DSP applications.

Disadvantages:

• Code Bloat: Empty operation slots are filled with NOPs, increasing the binary size dramatically (2–4× compared to RISC). This wastes instruction cache space and memory bandwidth.
• Poor Binary Compatibility: The instruction encoding is tightly coupled to the specific number and type of functional units. Changing the hardware (e.g., adding a new FP unit) requires recompiling all software. This is a massive practical barrier.
• Heavy Compiler Dependence: The compiler must do extremely aggressive optimization (trace scheduling, software pipelining, speculative execution). For irregular code (e.g., pointer-chasing, virtual dispatch), the compiler often cannot find enough parallelism.
• Cannot Adapt to Runtime Conditions: Unlike superscalar hardware that adapts dynamically to cache misses, branch patterns, and varying latencies, a VLIW schedule is fixed at compile time. A cache miss stalls the entire instruction.
• Difficult Exception Handling: Because multiple operations execute from one instruction word, determining which operation caused an exception and maintaining precise state is complex.

(c) Hurdles in Superscalar Performance [4]:

• Control Dependencies (Branches): Conditional branches occur every 5–7 instructions in typical code. Each branch creates a control hazard. Even with 95% branch prediction accuracy, the remaining 5% mispredictions flush the deep pipeline, wasting 15–20 cycles of speculative work each time. This is the single biggest limit on superscalar performance.
• Data Dependencies: True (RAW) data dependencies between instructions limit the number of independent operations available for parallel execution. Even with forwarding and out-of-order execution, chains of dependent instructions (e.g., pointer chasing) serialize execution.
• Hardware Complexity Wall: The wakeup-and-select logic in the instruction scheduler scales as O(n²) with the instruction window size. Doubling the issue width from 4-wide to 8-wide more than quadruples the scheduling hardware. At some point, the added complexity doesn't yield proportional IPC gains.
• Power Dissipation: The speculation engine, large register files, wide fetch units, and out-of-order logic consume massive power. Modern 6-wide superscalar cores reach 100+ watts, hitting thermal limits.
• Memory Wall: As processors get faster, the gap between CPU speed and memory latency widens. Cache misses cause long stalls that even deep instruction windows cannot hide.