Simple Answers & Key Points · 39 Questions
Benchmark programs are standardized applications, workloads, or suites of programs specifically designed to evaluate, measure, and compare the performance of different computer systems or components (like CPUs, GPUs, or memory).
Key Characteristics (Key Detail):
Measuring performance in computer architecture relies heavily on the perspective of the user versus the perspective of the system administrator. It is fundamentally measured using two main metrics: Execution Time and Throughput.
1. Execution Time (Response Time or Latency):
Execution Time(Y) / Execution Time(X) = n.2. CPU Execution Time:
3. Throughput (Bandwidth):
To determine which computer is faster, we must calculate the CPU Execution Time for both machines. Since they implement the exact same Instruction Set Architecture (ISA), the Instruction Count (IC) required to run the same program will be identical for both machines.
Step 1: State the Formula
Step 2: Calculate Execution Time for Computer A
Step 3: Calculate Execution Time for Computer B
Step 4: Compare and Calculate Speedup
Conclusion: Computer A is 1.2 times faster (or 20% faster) than Computer B.
Latency and Throughput are the two fundamental metrics used to define system performance, and they often trade off against one another.
Latency (Response Time):
Throughput (Bandwidth):
Relationship in Pipelining: Pipelining a processor increases Throughput (more instructions complete per clock cycle) but usually slightly degrades individual instruction Latency due to the overhead of pipeline registers and clock skew.
The performance of a computer system is not dictated by hardware alone; it is a complex interplay of hardware, architecture, and software. The classic CPU performance equation highlights three primary factors, but there are others:
These two terms are fundamental to understanding processor speeds and represent the base units of the CPU performance equation.
CPU Clock Time (Clock Cycle Time or Period):
Clock Cycle Time = 1 / Clock Rate.CPU Execution Time:
Total Cycles = Instruction Count × Average CPI, this expands to:Amdahl's Law is a fundamental principle in computer architecture used to find the maximum expected improvement (speedup) to an overall system when only a fraction of the system is improved.
The Core Concept:
The law states that the overall performance gain is strictly limited by the portion of the execution time that cannot be improved. You suffer from diminishing returns if you optimize only one part of the code while ignoring the rest.
The Formula:
Example Application:
Suppose a program spends 80% of its time doing floating-point (FP) math, and 20% doing integer logic. You invent a new FP unit that is 4 times faster.
Even though the FP unit is 4x faster, the overall system is only 2.5x faster because of the 20% unoptimized integer code. If S approached infinity, the max speedup is bounded by 1/(1-F) = 1/0.2 = 5x.
The Principle of Locality states that programs do not access all memory addresses uniformly; instead, they tend to access a relatively small portion of the address space at any given instant. This principle is the entire foundation upon which Cache Memory is built.
1. Temporal Locality (Locality in Time):
int i) or accumulators (e.g., sum += x) are accessed repeatedly over a short time span.2. Spatial Locality (Locality in Space):
A[i], it will soon access A[i+1]. Furthermore, programs execute instructions sequentially unless a branch occurs.In a pipelined processor, a Hazard is a condition that prevents the next instruction from entering its designated pipeline stage in the current clock cycle, necessitating a stall (pipeline bubble). There are three main classes of hazards:
1. Structural Hazards (Resource Conflicts):
2. Data Hazards (Data Dependencies):
ADD R1, R2, R3 (Writes to R1 in WB stage)SUB R4, R1, R5 (Reads R1 in ID stage)3. Control Hazards (Branch Hazards):
BEQ (Branch if Equal) instruction determines its target address and condition outcome in the EX or ID stage. By that time, 1 or 2 incorrect sequential instructions have already been fetched into the IF and ID stages and must be flushed.Data hazards (specifically Read-After-Write, or True Dependencies) occur when an instruction needs a value that is still flowing through the pipeline. They can be mitigated using three primary techniques:
1. Forwarding (or Bypassing):
2. Pipeline Interlocking (Hardware Stalls):
LOAD instruction fetches data in the MEM stage, but the very next instruction needs it in the EX stage. Forwarding goes backward in time, which is impossible.3. Compiler Instruction Scheduling (Software Solution):
Definition: In computer architecture, particularly in instruction pipelining, a hazard is a situation or condition that prevents the next instruction in the instruction stream from executing during its designated clock cycle.
Detailed Implications:
Processor designers and compiler writers use a combination of hardware and software techniques to handle hazards and minimize their performance impact:
Handling Structural Hazards:
Handling Data Hazards:
Handling Control Hazards:
Both data and structural hazards negatively impact pipeline performance by introducing stall cycles, which directly degrades the instruction throughput.
Mathematical Impact:
Effective CPI = Ideal CPI (1) + Stall Cycles/Instruction.Specific Impacts:
Branch prediction is a sophisticated optimization technique where the processor's hardware attempts to guess the outcome of a conditional branch (e.g., an if statement or a for loop condition) before the condition is actually evaluated in the execution stage.
How it works:
How it reduces control hazards:
Because modern dynamic branch predictors (like two-bit predictors or tournament predictors) achieve >95% accuracy, they effectively eliminate the vast majority of control hazard stalls.
Pipelining is an implementation technique where multiple instructions are overlapped in execution. It is analogous to an automobile assembly line: a car doesn't wait for the previous car to be completely finished before it starts; instead, different stations work on different cars simultaneously.
To achieve this, the execution of a single instruction is divided into distinct, isolated steps called stages. Each stage is separated by hardware registers (pipeline registers) to hold data between clock cycles.
The Classic 5-Stage RISC Pipeline:
(Note: This is a direct continuation and expansion of Question 15). In a classic 5-stage MIPS/RISC architecture, the stages operate precisely on the rising edge of the clock cycle:
By dividing execution into these 5 stages, a pipeline can process 5 different instructions simultaneously, one in each stage.
Implementing a robust, high-performance pipeline involves significant hardware complexity. Key challenges include:
Instruction pipelining is highly effective for RISC (Reduced Instruction Set Computer) architectures (like ARM or MIPS), but historically much less effective for CISC (Complex Instruction Set Computer) architectures (like older x86).
Reasons CISC impedes pipelining:
ADD R1, [Memory_Address]). This forces the instruction to undergo Address Calculation, Memory Fetch, AND Execution all within the same pipeline instruction flow, making it impossible to map neatly onto a standard 5-stage pipeline without massive stalls.Note: Modern x86 processors solve this by having a complex hardware decoder at the front-end that translates ugly CISC instructions into clean, RISC-like "micro-operations" (uOps) which are then pipelined efficiently.
Pipelining improves performance fundamentally by increasing Instruction Throughput—the number of instructions completing per unit of time—rather than decreasing the latency of any individual instruction.
The Mechanism of Improvement:
The Mathematical Result:
Ideally, an N-stage pipeline can yield a speedup of almost exactly N over a non-pipelined equivalent, multiplying overall CPU performance by N, simply by overlapping work that uses different hardware components.
Both utilize the concept of pipelining (breaking a task into sequential stages separated by registers), but they apply to entirely different levels of the processor hierarchy.
Instruction Pipelining:
Arithmetic Pipelining:
Data Forwarding (also known as bypassing or short-circuiting) is a critical hardware optimization used to resolve Read-After-Write (RAW) data hazards without stalling the pipeline.
The RAW Hazard Problem:
If Instruction A writes to R1, and Instruction B reads from R1, Instruction B normally has to wait until Instruction A completes its Write-Back (WB) stage. This would cause a 2- or 3-cycle stall.
How Forwarding Works (Details):
Branch prediction is a microprocessor technique that attempts to guess the outcome of a conditional branch (e.g., whether an 'if' statement is true or a loop will iterate again) before it is officially evaluated. This mitigates Control Hazards.
Static vs. Dynamic Prediction:
Reducing Control Hazards:
A structural hazard occurs when the hardware cannot support all the operations that the pipeline needs to execute simultaneously in a single clock cycle.
The Single Memory Problem (Von Neumann Architecture):
The Hazard Scenario:
If Instruction A (a Load) is in the MEM stage, it occupies the memory port to read data. In that exact same clock cycle, Instruction D (four cycles behind) is in the IF stage, trying to fetch its instruction word. They collide. The hardware must stall the IF stage (injecting a bubble) to let the MEM stage finish.
The Solution: Modern processors use a Harvard Architecture at the L1 cache level, providing a physically separate Instruction Cache (I-Cache) and Data Cache (D-Cache). This provides two independent memory ports, entirely eliminating this structural hazard.
Pipeline flushing (also called pipeline squashing or clearing) is the mechanism used by the processor to discard instructions that were speculatively fetched into the pipeline but should not be executed.
When does flushing occur?
Mechanism (How it works):
This is a classic performance calculation requiring comparison of execution times between a non-pipelined and pipelined processor.
Parameters:
1. Non-Pipelined Execution Time:
2. Pipelined Execution Time:
3. Speedup Calculation:
Conclusion: The pipelined processor achieves a speedup of ~4.8x over the non-pipelined equivalent. (Notice how this approaches the theoretical maximum speedup of k = 5).
To calculate pipeline efficiency, we must determine the Ideal CPI and the Actual Effective CPI considering the branch penalties.
Parameters:
1. Calculate Stall Cycles per Instruction:
2. Calculate Actual Effective CPI:
3. Calculate Pipeline Efficiency:
Conclusion: The pipeline efficiency is 90.9%. This means the processor achieves 90.9% of its theoretical maximum throughput.
Note: You can draw a pipeline timing diagram to show how hazards are resolved. Let's assume the following common sequence demonstrating a RAW hazard:
1. ADD R1, R2, R3 (Writes to R1)
2. SUB R4, R1, R5 (Reads R1)
Scenario A: Without Forwarding (Hardware Interlock)
The ADD writes R1 in cycle 5 (WB). The SUB needs R1 in cycle 3 (ID). The hardware must stall SUB for 2 cycles.
Cycle: 1 2 3 4 5 6 7 8
ADD IF ID EX MEM WB
SUB IF ID [stall] [stall] EX MEM WB
The pipeline wastes 2 cycles (bubbles) waiting for the register file to update.
Scenario B: With Forwarding (Bypassing)
The ADD computes the result of R1 at the end of cycle 3 (EX stage). The SUB needs R1 at the beginning of its EX stage (cycle 4). Forwarding hardware routes the ALU output directly back to the ALU input.
Cycle: 1 2 3 4 5 6
ADD IF ID EX MEM WB
SUB IF ID EX MEM WB
The SUB executes smoothly without stalling. The data is forwarded from the EX/MEM pipeline register to the ALU input multiplexer in Cycle 4.
This calculation requires understanding how stalls artificially inflate the Cycles Per Instruction (CPI).
Parameters:
Calculation Steps:
The average penalty spread across all instructions is calculated by multiplying the frequency of the hazard by the penalty of the hazard.
Now, add this penalty to the base ideal CPI.
Conclusion: The effective CPI of the processor under these conditions is 1.4. It takes 1.4 clock cycles, on average, to retire an instruction.
While often used interchangeably in a casual context, computer architecture makes a strict distinction between the two based on their origin, synchronicity, and handling behaviour.
| Feature | Exceptions | Interrupts |
|---|---|---|
| Origin | Generated internally by the CPU as a direct result of executing the current instruction. | Generated externally by hardware/peripheral devices (I/O) outside the CPU. |
| Synchronicity | Synchronous: They occur at the exact same instruction boundary every time the program runs with the same data. | Asynchronous: Can occur at any random/unpredictable instruction boundary, independent of the code. |
| Handling | Must be handled immediately before proceeding, as the faulting instruction cannot complete execution. | The CPU typically finishes the current instruction in the pipeline, saves state, and then services it. |
| Program Counter (EPC) | EPC points to the faulting instruction itself (so it can be re-executed after correcting the exception). | EPC points to the next instruction to execute when the program resumes. |
| Examples | Divide-by-zero, page fault, arithmetic overflow, invalid opcode, memory protection violation. | Keyboard keystroke, mouse movement, network packet arrival, hardware timer expiration. |
The Status Register (also known as the Condition Code Register or Flags Register) is a crucial hardware register containing a set of boolean flags. It is vital for control flow and system state management.
Primary Functions:
Branch if Equal or Branch if Less Than) do not perform math themselves. They simply look at the flags set by a previous comparison instruction to decide whether to take the branch. Without the status register, loops and if-statements cannot function.These are the two primary mechanisms a processor uses to figure out which device caused an interrupt and how to handle it.
| Feature | Polled Interrupts (Software-Driven) | Vectored Interrupts (Hardware-Driven) |
|---|---|---|
| Mechanism | All devices share a single interrupt request line. The CPU jumps to one central, general-purpose Interrupt Service Routine (ISR). | Each device sends a unique identifier code called the Interrupt Vector over the data bus during interrupt acknowledgment. |
| Identification | The ISR executes a software loop, checking (polling) the status register of each attached device sequentially. | The CPU uses the vector code as an index into the Interrupt Vector Table in memory to find the specific ISR address directly. |
| Speed & Efficiency | Slow. Software polling loop wastes CPU clock cycles querying idle devices. | Extremely fast. Direct hardware mapping jumps to the target ISR instantly without scanning. |
| Hardware Cost | Very simple and cheap. No extra hardware logic needed. | Complex. Requires a dedicated Interrupt Controller to handle vector generation and priorities. |
| Scalability | Poor. Polling delay increases linearly as more devices are added. | Excellent. Scalable to many devices with low overhead. |
The process of an exception taking place and being handled is a highly coordinated dance between the hardware pipeline and the operating system software.
The Step-by-Step Mechanism:
Exceptions are catastrophic to pipeline throughput. They violate the core assumption of pipelining: a steady, uninterrupted flow of instructions.
Impact on Performance:
Mechanisms to Minimize Loss:
In a pipelined processor, multiple instructions are executing simultaneously in different stages. It is entirely possible for an instruction in the MEM stage to cause a page fault in the exact same clock cycle that an instruction in the IF stage causes a memory protection violation.
The Rule of Precise Exceptions (Program Order):
To maintain architectural correctness, exceptions must be handled in the exact logical order the instructions appeared in the original program, regardless of when the hardware detected them.
How Hardware Manages Priority:
Both are critical for preserving the state of the machine so the Operating System can diagnose the issue and potentially resume the interrupted program.
Role of the Program Counter (PC):
Role of the Register File:
To design a robust system that handles multiple simultaneous exceptions while maintaining "precise exceptions," you must decouple the detection of an exception from the handling of the exception.
The Hardware Design (Details):
Example Scenario: Arithmetic Overflow.
Consider the instruction sequence:
1. ADD R1, R2, R3 (Causes overflow in EX stage)
2. SUB R4, R5, R6 (Currently in ID stage)
3. AND R7, R8, R9 (Currently in IF stage)
Step-by-Step Handling Process:
ADD instruction is in the EX stage. The ALU adds R2 and R3 and detects that the result is too large to fit in 32 bits. The ALU hardware raises the Overflow signal.ADD instruction.ADD moves to MEM. The SUB moves to EX. The AND moves to ID.ADD moves to WB. The hardware in the WB stage checks the exception bits. It sees the Overflow bit is set.ADD from writing its corrupted result to R1.SUB, AND, and any newer instructions into NOPs, throwing them away.ADD instruction is loaded into the EPC register.Out-of-Order (OoO) execution massively complicates exception handling. It breaks the fundamental requirement for Precise Exceptions.
The Problem (Imprecise Exceptions):
In an OoO processor, Instruction 5 might execute and complete before Instruction 2 (because Instruction 2 was waiting for a slow memory fetch). If Instruction 2 eventually causes a Page Fault, the machine state is corrupted: Instruction 5 has already written its results to registers. The OS cannot easily restart the program because the processor is in an inconsistent, non-sequential state.
The Solution: The Reorder Buffer (ROB)
Modern OoO processors solve this using a hardware structure called a Reorder Buffer.
Delayed Exception Handling (often used in conjunction with Speculative Execution or VLIW architectures) is a technique where an exception is detected but intentionally ignored or deferred until a later point in the program.
Why do it?
Modern processors heavily use Speculative Execution (guessing a branch outcome and executing instructions down that path before knowing if the guess was right). If a speculative instruction causes an exception (e.g., reading an invalid memory address), the processor shouldn't crash the program immediately—because it might turn out that the branch was mispredicted and that instruction was never supposed to execute anyway!
How it works (Poison Bits):